Roles and Responsibilities

• Complex SOC Top Physical Implementation for next generation SOCs in area of mobile application processors, modem sub-systems and connectivity chips by means of Synthesis, Place and Route, STA, timing and physical signoffs
• Hands on experience doing physical design and timing closure of complex blocks and full-chip designs
• Experience in top level floor planning including partition shaping and sizing, pin placement, channel planning, high speed signal and clock planning and feed-through planning is a plus
• Should have strong understanding of timing, power and area trade-offs and optimization of PPA
• Power user of industry standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities
• Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows
• Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ
• Expertise in block level and full-chip SDC clean up, Synthesis optimization, Low Power checking and logic equivalence checking
• Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling)
• Familiar with typical SOC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions
• Familiar in hierarchical design, top-down design, budgeting, timing and physical convergence
• Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level
• Should have gone through recent successful SOC tape-outs

Experience 5+ Years of experience

Qualifications

• B.Tech/B.E/M.Tech/M.E